A configurable circuit where a plurality of logic blocks are connected in a programmable wire structure, such as a Field Programmable Gate Array (FPGA) or a Programmable Logic Device (PLD), has been widely used.
FIG. 1 is a block diagram illustrating a configuration example of a related FPGA. The FPGA is composed of arrangements of programmable cells 201—x (x is an integer). Although the arrangements are normally two-dimensional, FIG. 1 shows one-dimensional arrangements as a part.
For example, like programmable cell 201_1, each of the programmable cells includes programmable logic block 4, wire group 10, programmable switches 2x—y (x and y are integers), and input selectors 3—x (x is an integer). As illustrated in FIG. 1, programmable cell 201_1 includes programmable switches 21_1, 21_2 and 22_2 and input selectors 3_1 and 3_2. Programmable logic block 4 has a plurality of input terminals (A and B of FIG. 1) and output terminal C, and realizes a variety of logic functions based on data (configuration data) recorded on a configuration memory (not shown).
Wire group 10 is to transmit data between different programmable cells. Programmable switch 2x—y connects wire 1x—y or output terminal C of programmable logic block 4 to an adjacent wire, or disconnects the adjacent wires (x and y are integers). Input selector 3—x (x is an integer) selects a signal transmitted via one wire of wire group 10, and supplies the selected signal to the input terminal (A and B of FIG. 1) of programmable logic block.
FIG. 2 is a block diagram illustrating a configuration example of related programmable switch 2x—y (x and y are integers). This switch executes any one of the following three functions according to configuration data.
Select a signal input to any one of terminals T0 and T using selector 3_4, and output the signal to terminal T1 via tristate buffer 5_2.
Select a signal input to any one of terminals T1 and T using selector 3_3, and output the signal to terminal T0 via tristate buffer 5_1.
Disconnect terminals T0 and T1.
Generally, in the FPGA, wire group 10 is composed of plural kinds of wires. FIG. 1 shows an example in which wire group 10 is composed of short distance wire group 11 and long distance wire group 12. Short distance wire group 11 has a length equivalent to a width of the programmable cell, and is appropriate for signal transmission between the neighboring programmable cells. Long distance wire group 12 has a length equivalent to two widths of the programmable cell, and is appropriate for signal transmission between the programmable cells spaced apart from each other over two cells.
Actually, since ‘delay of short distance wire<delay of long distance wire’ is satisfied, connecting adjacent cells via the short distance wire is advantageous in terms of signal transmission. On the other hand, since ‘delay of short distance wire×2>delay of long distance wire’ is satisfied, connecting the cells spaced apart over two cells via the long distance wire rather than the short distance wire is advantageous in terms of signal transmission.
As described above, plural kinds of wires should be prepared to accomplish high speed signal transmission. Although FIG. 1 shows two kinds of wires for simplification, actually, more kinds of wires are necessary. Accordingly, the number of the wires increases, so that the area of the programmable cell increases.
In addition, since it is necessary to have the same number of programmable switches 2x—y as wires, they occupy a large area. Particularly, since tristate buffers (5_1 and 5_2 of FIG. 2) in programmable switch 2x—y annexed to the long distance wire need a large driving force, they also occupy a large area.
Recently, a switch element (hereinafter, referred to as Memory-type low resistance switch element) was developed which can programmably set a high resistance state and a low resistance state, can memorize the set state to be non-volatile, and which has a much lower ON resistance than a MOS transistor of the same occupancy area. An example has been disclosed in Japanese Laid-Open Patent Publication No. 2005-101535. FIG. 3 shows a configuration example of the switch element.
As illustrated in FIG. 3, the memory-type low resistance switch element includes metal electrode 60 which is difficult to ionize, metal electrode 62 which is easy to ionize, and electrolyte 61. Both metal electrodes are connected or disconnected according to a method for applying a voltage between metal electrode 60 which is difficult to ionize and metal electrode 62 which is easy to ionize. Since a resistance of connection of these electrodes is much lower than that of the MOS transistor of the same occupancy area (by over a number of one cipher), it is possible to realize a high performance switch with a small area. Moreover, since the connection or disconnection state once formed is maintained for a certain period of time, memory for memorization is not necessary. As a result, a circuit using the memory-type low resistance switch element can be implemented in a smaller area than a circuit which does not use the same.
In the meantime, there are different kinds of memory-type low resistance switch elements. An example of different kinds of switch elements has been disclosed in Japanese Laid-Open Patent Publication No. 2005-317978.